Automated design of combinatorial logic circuits

This paper deals with automated design of combinatorial circuits with the use of Cartesian Genetic Programming (CGP). The synthesis is based on user specifications of network functionality, while the network structure may be predefined. The results show that CGP approach is able to match the desired functionality while preserving other performance criteria, such as latency and number of gates. Additionally, the evolution process may use Verilog network descriptions as input files, which facilitates the design for larger number of inputs and test patterns.