Performance trade-offs and design limitations of analog-to-information converter front-ends

This paper evaluates the impact of circuit impairments on the energy cost and performance limitations of analog-to-information converters (AIC). In applications where signal frequencies are high, but information bandwidths are low, AICs have been proposed as a potential solution to overcome the resolution and performance limitations of sampling jitter in high-speed analog-to-digital converters (ADC). Although the AIC architecture facilitates slower ADCs, the signal encoding, typically realized with a mixer-like circuit, still occurs at the Nyquist frequency of the input to avoid aliasing. We show that the jitter of this mixing stage limits the achievable AIC resolution. In this work, the end-to-end system evaluation framework is designed to analyze these limitations as well as the relative energy-efficiency of AICs versus ADCs across the resolution, receiver gain and signal sparsity. The evaluation shows that AICs improve the resolution by 1 bit when the signal of interest is very sparse, and enable 2× in energy savings when no pre-amplification is required.