A high speed serial bus controller ASIC

A fully automated design flow of a high speed serial bus controller ASIC with asynchronous data transfer is presented. The whole chip including not only the control state machine and the /spl mu/Processor interface, but also the synchronising unit has been designed using VHDL. For verification and synthesis the SYNOPSYS tool set was used, the back-end design steps were accomplished using a technology independent placement and routing tools (EPOCH by CASCADE). It could be proven that both control state machines running comparably low frequencies and units running at high system speeds are equally well suited for a fully automated design approach. All user specifications were met, special emphasis was put on Design For Testability (DFT) which resulted in an overall fault coverage of more than 95%.