Title :
Symbolic oriented stuck fault modeling of CMOS sequential circuits
Author :
P.M. Petkovic;D.P. Milovanovic;V.A. Zivkovic
Author_Institution :
Fac. of Electron. Eng., Nis Univ., Serbia
Abstract :
This paper presents a new method for stuck fault modeling of CMOS sequential circuits at transistor level. The method is based on the application of Transistor Logic Conductance Functions (TLCF) which are obtained using symbolic simulation. Multiple faults can also be modeled with our approach. Finally, the application of the TLCF for test pattern generation is included.
Keywords :
"Circuit faults","Semiconductor device modeling","Sequential circuits","CMOS logic circuits","Circuit simulation","MOSFETs","Logic circuits","Variable structure systems","Switches","Combinational circuits"
Conference_Titel :
Microelectronics, 1997. Proceedings., 1997 21st International Conference on
Print_ISBN :
0-7803-3664-X
DOI :
10.1109/ICMEL.1997.632962
