Modeling event-driven successive charge redistribution in ADC with varying rate of charge transfer

The paper addresses a technique of the asynchronous (clockless) analog-to-digital conversion based on the event-driven successive charge redistribution (SCR) in the binary-scaled capacitor array. A significant point is that the event-driven SCR-ADC differs from the known techniques of charge redistribution used in classical ADCs with the binary-weighted capacitors because the charge transfer is self-timed in the former whereas it is clock-driven in the latter. Former publications on event-driven SCR-ADC were based on constant-rate charge redistribution between the source and the destination capacitors realized by the current source in the number of steps defined by converter resolution. The contribution of the present study is the analysis of the event-based SCR scheme forced by voltage difference between both capacitors which decreases as the charge redistribution proceeds. The aim of the analysis is the evaluation of the conversion time of the relevant converter.