3649789

A Design Methodology For The High-level Synthesis Of Fault-tolerant Asics

A. Orailoglu;R. Karri

University of California, San Diego

1992

6/14/1905 12:00:00 AM

417

426

"Design methodology","High level synthesis","Fault tolerance","Application specific integrated circuits","Costs","Fault tolerant systems","Space technology","Computer science","System-on-a-chip","Large-scale systems"

ieee

VLSI Signal Processing, V, 1992., [Workshop on]

0-7803-0811-5

conf

10.1109/VLSISP.1992.641073

641073