DocumentCode :
3650010
Title :
Planar and 3D Ge FETs
Author :
C. W. Liu;Hung-Chih Chang;Cheng-Ming Lin;Yen-Ting Chen
Author_Institution :
Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan
fYear :
2012
Firstpage :
1
Lastpage :
4
Abstract :
The strain response of high mobility Ge nFETs, low EOT (~1 nm) ZrO2 Ge nFETs, and triangular Ge pFinFETs are reported. The strain response of (111) substrates is smaller than (001) substrates under tensile strain along <;110> channel direction. Low EOT gate-last Ge nFETs using ZrO2 gate dielectric with nearly no interfacial layer is demonstrated with the superior electrical performance. Moreover, the triangular Ge GAA pFinFET with fin width (Wfin) of 52nm and Lg of 183nm has Ion/Ioff = 105, SS= 130mV/dec, and Ion=235 A/m at -1 V. T he dislocated Ge near Ge/Si interface on SOI was etched and formed nearly defect-free channels.
Keywords :
"Substrates","Silicon","MOSFET circuits","Logic gates","Tensile strain","FETs"
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Print_ISBN :
978-1-4673-2474-8
Type :
conf
DOI :
10.1109/ICSICT.2012.6467609
Filename :
6467609
Link To Document :
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