DocumentCode :
36503
Title :
IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test
Author :
Li, Katherine Shi-Min ; Yi-Yu Liao
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Volume :
21
Issue :
7
fYear :
2013
fDate :
Jul-13
Firstpage :
1333
Lastpage :
1337
Abstract :
On-chip interconnect structures become much more complicated and dominate system performance in multicore system-on-chips. Oscillation ring (OR) test is an efficient test method for most types of faults in the interconnect structures, and previous studies show that both 100% fault coverage and the optimum diagnosis resolution for various fault models are achievable. The cost of OR test is decided by the number of test sessions required to form all the rings. Previous ring generation algorithm tries to generate long rings that usually cannot be put into the same test session, and thus the number of test sessions is not necessarily smaller. In this brief, we study techniques to generate rings that can be tested concurrently, so that the overall test time can be reduced significantly.
Keywords :
electron device testing; microprocessor chips; multiprocessing systems; system-on-chip; IEEE 1500 compatible multilevel maximal concurrent interconnect test; dominate system performance; fault model; multicore system on chips; onchip interconnect structures; optimum diagnosis resolution; oscillation ring test; ring generation algorithm; test session; Circuit faults; Integrated circuit interconnections; Multicore processing; Oscillators; Parallel processing; Partitioning algorithms; Interconnect; multicore; multilevel framework; oscillation test; system-on-chips (SoCs); test parallelism;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2012.2210451
Filename :
6289380
Link To Document :
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