A low noise and low loss power MOSFET with low Vth regions for voltage regulators

A novel low voltage power MOSFET with a low threshold voltage (Vth) region (sub-MOS) is proposed. The proposed MOSFET has a superior trade-off relationship between output efficiency and switching noise, with a spike voltage 82% lower than a conventional MOSFET and the same efficiency at 300 kHz with an output current of 20 A. Since the proposed device reduces the drain current through rate (dir/dt) by false turn-on of the sub-MOS, it decreases the spike voltage during diode reverse recovery. The false turn-on losses are suppressed by the saturation current of the sub-MOS, which is controlled by optimizing the sub-MOS area and the Vth. The low on-state resistance of sub-MOS compensates for the false turn-on losses to achieve high efficiency.