Test-TSV estimation during 3D-IC partitioning

Three dimensional integrated circuits (3D-ICs) are emerging as a viable solution to the interconnect scaling problem. During early design space exploration, a large number of possible partitioning solutions are evaluated w.r.t. performance, area, through-silicon-via (TSV) count, etc. During this evaluation process, the number of test-TSVs need to be added to the total TSV count, to prevent unexpected area overhead later on in the design flow. While a fixed test-TSV count may provide sufficient guardbanding, in this paper we show that it often overestimates the actual number of test-TSVs required. Currently, the only way to determine the pareto-optimial test-TSV count is to sweep the test-TSV constraint, and repeatedly apply 3D test architecture optimization algorithms. This process is time consuming, and is too slow to be used in automated partitioning. In this paper, we present a quick and accurate estimation of the pareto-optimal number of test-TSVs required for a given partition. This can be used as an input to the partitioner to quickly estimate the total number of TSVs used for a given partition, reducing over-design.