On the implementation of a three-operand multiplier

A new approach for a three-operand multiplier is proposed, using initial two-level radix-4 recoding, in order to reduce the cost and delay of other utilized methods. A three-operand 4-bit multiplier is demonstrated as a model, and serves as a building block for three-operand multipliers of higher precision. The proposed method is shown to yield a significant reduction in both the cost and delay of a three-operand 4-bit multiplier.