DocumentCode :
3652552
Title :
Precision improvement in current-mode winner-take-all circuits using gain-boosted regulated-cascode CMOS stages
Author :
B. Sekerkiran;U. Cilingiroglu
Author_Institution :
Dept. of Electron. & Telecommun., Istanbul Tech. Univ., Turkey
Volume :
1
fYear :
1998
Firstpage :
553
Abstract :
This paper presents a study on advantages and concerns of using gain-boosted regulated-cascoding technique in current-mode winner-take-all (WTA) circuits. For large scale integration and high frequency applications the use of MOS transistors with minimum feature size is a must. However, modern MOS transistors with sub-micron channel length exhibit pronounced channel-length modulation. This deficiency causes precision degradation in WTA circuits. With the use of gain-boosted regulated cascoding technique, a very high precision can be achieved in current-mode WTA circuits formed using sub-micrometer transistors.
Keywords :
"MOSFETs","Voltage","CMOS technology","Time of arrival estimation","Application specific integrated circuits","Large scale integration","Frequency","Degradation","Feedback circuits","Joining processes"
Publisher :
ieee
Conference_Titel :
Neural Networks Proceedings, 1998. IEEE World Congress on Computational Intelligence. The 1998 IEEE International Joint Conference on
ISSN :
1098-7576
Print_ISBN :
0-7803-4859-1
Type :
conf
DOI :
10.1109/IJCNN.1998.682327
Filename :
682327
Link To Document :
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