DocumentCode :
3652654
Title :
An all-digital delay-locked loop for high-speed memory interface applications
Author :
Shih-Lun Chen;Ming-Jing Ho;Yu-Ming Sun;Maung Wai Lin;Jung-Chin Lai
Author_Institution :
Memory Interface Department, IP Research and Development Division, Global Unichip Corporation (GUC), Taiwan
fYear :
2014
fDate :
4/1/2014 12:00:00 AM
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents an all-digital delay-locked loop with the novel digital delay line for high-speed memory interface applications. The proposed digital delay line has smaller tuning step and better tuning linearity than the prior arts. The proposed ADDLL inside the DDR3 PHY for the purpose of the 90-degree phase shift and read leveling is fabricated in a 40nm low-power CMOS process. The testchip is successfully verified at the data rate of 800∼1600Mbps. The measured peak-to-peak and rms jitter of the write DQS are 60ps and 10ps at the data rate of 1600Mbps, respectively.
Keywords :
"Delays","Delay lines","Tuning","Inverters","Jitter","CMOS process","System-on-chip"
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on
Type :
conf
DOI :
10.1109/VLSI-DAT.2014.6834900
Filename :
6834900
Link To Document :
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