An Architecture Model for Harvesting-Aware Applications in FPGA

This paper describes a novel scalable architecture model for the design of harvesting-aware applications on FPGAs. The objective of the proposed approach is to reduce the additional design complexity inherent to this type of design. The adopted strategy was to adapt the energy consumption of the system by controlling the toggle rate of its signals according to the energy prediction and the performance levels set by the system designer. The architecture model was designed in a Cyclone IV FPGA and its main advantages are: it may be used within a wide range of applications, since it has been modelled to control synchronous systems, it causes a little impact on the project design, as to couple the harvesting-aware subsystem with the application modules does not imply changes in the application source code. In the case study presented, an RGB-YCbCr converter was used as an application in order to validate the implementation data, simulation and results presented in this paper.