• DocumentCode
    3658781
  • Title

    Automatic register balancing in model-based high-level synthesis

  • Author

    Chandan Karfa

  • Author_Institution
    Synopsys (India) Pvt. Ltd, Bangalore, India
  • fYear
    2015
  • Firstpage
    43
  • Lastpage
    49
  • Abstract
    The designer sometimes wants to insert register(s) in specific location(s) of a design in order to break critical paths. To do so, the designer has to manually insert registers in all parallel paths as well to balance registers in all paths to keep the functionality of the design intact. This task is known as `register balancing´ in the design community. The design size, complexity and hierarchy make manual register balancing in parallel paths task complex and error prone. The method presented here automatically inserts register(s) in the user specified location(s) and also automatically balances registers in all parallel paths. The register balancing problem has been suitably mapped to global retiming problem and solved using standard global retiming algorithm. The proposed method has been implemented in a model based high-level synthesis tool and tested on several Simulink designs.
  • Keywords
    "Registers","Clocks","Delays","Integrated circuit modeling","Software packages","Libraries","Mathematical model"
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ASQED), 2015 6th Asia Symposium on
  • Type

    conf

  • DOI
    10.1109/ACQED.2015.7274005
  • Filename
    7274005