Implementation of S-Box for Advanced Encryption Standard

This paper presents implementation of S-Box for Advanced Encryption Standard (AES) algorithm. The proposed design structure is implemented in verilog. Previous works rely on lookup tables to implement the S-Box of AES algorithm which incurred a fixed and unbreakable delay. The proposed design employs combinational logic based composite field arithmetic AES S-Box which results in optimized area in terms of FPGA slices compared to ROM based lookup table. The proposed 4-stage pipelined implementation of S-Box is carried on the XC3S100E device of Xilinx FPGA with verilog code which requires 34 slices and 67 4-input LUTs and also maximum clock frequency of 187.071 MHz.