• DocumentCode
    3659144
  • Title

    Additional charge trapping layer SONOS nonvolatile memory based on ultra-thin body poly-Si junctionless FinFET

  • Author

    Wei-Cheng Wang;Chien-Chih Chung;Ming-Hsien Chung;Cheng-Ping Wang;Yung-Chun Wu

  • Author_Institution
    Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan
  • fYear
    2015
  • fDate
    6/1/2015 12:00:00 AM
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    This work demonstrates ultra-thin body (UTB) trench structure Junctionless FinFET (trench JL-FinFET) with double stacked Si3N4 charge trapping layer (NN-CTL) Si-SiO2-Si3N4-Si3N4-SiO2-Si (SONNOS) nonvolatile memory (NVM). It shows excellent memory characteristics, high program/erase (P/E) performance, good endurance (>104 cycles) and an excellent 10 years data retention with 99% electron remaining at 85°C.
  • Keywords
    "Nonvolatile memory","FinFETs","Logic gates","Performance evaluation","SONOS devices","Charge carrier processes","Silicon"
  • Publisher
    ieee
  • Conference_Titel
    Silicon Nanoelectronics Workshop (SNW), 2015
  • Type

    conf

  • Filename
    7275278
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3659144