Hybrid channel poly-Si junctionless field-effect transistors with trench structure formed by dry etching process

This work demonstrates p-type hybrid poly-Si fin channel junctionless field-effect transistor (JL-FET) with trench structure by dry etching process. This JL-FET shows superior performance in a low drain-induced barrier lowering (<;10mV/V) and high I_on/I_off (>10⁸) for L_eff = 1μm, excellent gate control.