Characteristics of inversion, accumulation and junctionless mode silicon N-type and P-type bulk FinFETs with optimized 3-nm nano-fin structure

We for the first time evaluate the 3-nm gate Length (L_G=3nm) inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode Silicon bulk FinFET performance with optimized nano-fin structure (F_W=F_H=3nm) using 3-D quantum transport device simulation. The excellent electrical characteristics of L_G=3nm Si bulk FinFET are reported. The sub threshold slope values (SS~65mV/dec.) and drain-induced barrier lowering (DIBL<;17mV/V) are analyzed in all three IM, AC and JL modes bulk FinFET with |V_TH| ~0.31 V. This research reveals that Moore´s law can be scaled down to 3-nm nodes.