• DocumentCode
    3659180
  • Title

    A capacitance-voltage model for DG-TFET

  • Author

    Arnab Biswas;Adrian M. Ionescu

  • Author_Institution
    Ecole Polytechnique Fé
  • fYear
    2015
  • fDate
    6/1/2015 12:00:00 AM
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    In this work we develop a simplified capacitance model for Double Gate TFETs. Capacitance-voltage measurements were done on all-Silicon SOI TFETs at different biasing schemes to support the model development. TCAD simulations [1] of DG-TFETs were used to validate the model.
  • Keywords
    "Logic gates","Capacitance","Computational modeling","Capacitance measurement","Biological system modeling","Voltage measurement","Current measurement"
  • Publisher
    ieee
  • Conference_Titel
    Silicon Nanoelectronics Workshop (SNW), 2015
  • Type

    conf

  • Filename
    7275314
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3659180