Title :
Performance evaluation of Si ultra-thin body (1 nm) junctionless FET with LG = 1 nm and LG = 3 nm
Author :
Yi-Ruei Jhan;Yan-Bo Liu;Yung-Chun Wu
Author_Institution :
Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan
fDate :
6/1/2015 12:00:00 AM
Abstract :
A Si ultra-thin body (UTB) junctionless field-effect transistor (UTB-JLFET) with LG = 1 nm and LG = 3 nm have been demonstrated by solving the coupled drift-diffusion (DD) and density-gradient (DG) model. The simulation results show that the Si can be used in ultra-short channel device as long as UTB is employed. As UTB is employed, ultra-short channel device does not need to follow an empirical rule of Tch = LG / 3. Furthermore, UTB-JLFET 6T-SRAM cell has reasonable static noise margin (SNM) value of 138 mV. The circuit performances reveal UTB-JLFET can be used for sub-5 nm CMOS technology nodes.
Keywords :
"Silicon","Logic gates","Performance evaluation","Timing","Inverters","CMOS integrated circuits","Potential well"
Conference_Titel :
Silicon Nanoelectronics Workshop (SNW), 2015