FSMD RTL design manipulation for clock interface abstraction

The rapid raise of embedded systems design complexity and size has emphasized the importance of high-performance simulation models. This has resulted in emergence of design methodologies at the higher levels of abstraction such as Electronic System Level (ESL) and Transaction Level Modelling (TLM) and SystemC language as the main instrument. In practice, system architects and system integrators often have access to a library of legacy Register Transfer Level (RTL) HW IP cores or obtain new ones from IP design houses. To address simulation performance, such RTL IP cores are manually recreated at more abstract levels, which implies significant tedious and error-prone effort. The current paper addresses this problem by proposing a novel approach for automated FSMD RTL design manipulation for clock interface abstraction. The manipulation approach takes as an input FSMD (Finite State Machine with datapath embedded) RTL design in VHDL and transforms it to an equivalent Algorithmic State Machine (ASM) representation in SystemC with explicit separation of design functionality by states. Finally, the clock interface is abstracted up to optimize the simulation performance. The manipulation details are demonstrated on a case study design and the first experimental results show simulation speed-up and prove feasibility of the proposed approach.