Design and implementation of sample and hold circuit in 180nm CMOS technology

This project presents the implementation of error reduction techniques in sample and hold circuit(S/H).S/H suffers from multiple errors such as droop, acquisition error, aperture jitter, etc. Mainly two hold mode errors that is charge injection and clock feedthrough. We are trying to mitigate these errors by using different design techniques. When a switch in the S/H turns on, the capacitor starts charging and discharges when it turns off. Due to this action the sampled output signal may suffers from attenuation that is called charge injection. Due to the some overlap capacitance of gate and drain clock feed through error may also occur. This paper presents designing different S/H architectures to reduce these errors and also gives high gain, more stable, increased acquisition range, low power consumption. The proposed architectures are designed in 180nm CMOS Technology with input sinusoidal frequency 10MHz and 1V P-P. Sampling rate is 500MHz. The design is target to gain of 65dB.