Bus bandwidth monitoring, prediction and control

With the introduction of Dynamic voltage/ frequency scaling (DVFS), the supply voltage to the various components on System-on-Chip (SoC) can be controlled depending on system load to track power-performance curve for best possible efficiency. Although dynamic power management solutions like DVFS for CPU and GPU are quite common and implemented in almost every embedded device, unfortunately the same is not true about the bus fabric interconnecting different subsystems on a SoC infrastructure. Due to inherent shared nature of the bus and hardware complexities, it is either operated at fixed frequency by targeting the maximum load case scenario or at varied frequency, using a static lookup table based on processor frequencies. In this paper we analyze the shortcoming of the later approach and propose a real-time bus bandwidth prediction of the bus connected to Processor cores using Hardware Performance Counters(HPCs) and block layer in Operating system to address them.