Multi-objective optimization for VLSI implementation of Artificial Neural Network

Neural Network´s capability to mimic the structures and operating principles found in the information processing systems possessed by humans & other living creatures has made today Artificial Neural Network (ANN) a technical folk legend. The main hurdle in the VLSI implementation of neural network (NN) is that either the design can be area efficient or power efficient or speed efficient; but not all area-time-speed efficient simultaneously. Optimizing one parameter affects the other. At the same time NN also demands that the design should have high degree of precision and dynamic range which makes multi-objective optimization of VLSI implementation of neural network (NN) a complex goal. In this paper an optimal multi-objective optimization approach for VLSI implementation of feed forward neural network has been suggested. Simulation results with 45 nm & 90 nm tech file on Synopsis Design Vision Tool, Aldec´s Active HDL tool, Altera´s Quartus tool & MATLAB showed that the bit serial architecture (TYPE III) based multiplier implementation and use of floating point arithmetic (IEEE -754 Single Precision format) in ANN realization may provide a good multi-objective solution for VLSI implementation of ANN.