An ASIP-based control system for Vision Chips with highly parallel signal processing

The field of Machine Vision is still dominated by classical imaging systems consisting of a camera attached to a PC. Especially very fast processes with high requirements on minimal latency or maximal refresh rate are increasingly starting to stretch such systems to their limits. Image sensors with integrated feature extraction - so-called “Vision Chips” - already allow reducing the amount of data on chip compared to conventional imagers, thereby narrowing down the output to relevant data. Freely programmable systems are not restricted to the execution of a specific hard-wired algorithm. However, not least because of the necessary, but rather complex external circuitry, none of the proposed systems have so far been able to gain acceptance. This paper introduces an architecture of an Application-Specific Instruction Set Processor (ASIP) based control system, which can be directly incorporated into a System-on-Chip (SoC). The sensor´s functional units are integrated into the micro-controller as additional data path elements, making them directly accessible as part of the instruction set. Furthermore, a parameterizable input/output (IO) controller and an Serial Peripheral Interface (SPI) based configuration interface enable the system to be used widely self-sufficient with specific algorithms. The proposed control system has been integrated into a prototypical Vision Chip and has been successfully tested.