• DocumentCode
    3662311
  • Title

    Value analysis for the determination of memory instruction latency in a WCET tool

  • Author

    Karila Palma Silva;Renan Augusto Starke;Rômulo Silva de Oliveira

  • Author_Institution
    Department of Systems Automation, Fed. Univ. Santa Catarina (UFSC), Florianó
  • fYear
    2015
  • fDate
    7/1/2015 12:00:00 AM
  • Firstpage
    252
  • Lastpage
    257
  • Abstract
    This paper presents a method to determine the latency of memory instructions, aimed for use in WCET tools. We use a technique known as value analysis. Considering a processor with different data memory latencies, value analysis is used to determine the possible values of processor registers statically, allowing the recognition of memory addresses (main memory or ScratchPad Memory) in order to obtain tighter WCET upper bounds.
  • Keywords
    "Registers","Random access memory","Analytical models","Timing","Real-time systems","Process control","Pipelines"
  • Publisher
    ieee
  • Conference_Titel
    Industrial Informatics (INDIN), 2015 IEEE 13th International Conference on
  • ISSN
    1935-4576
  • Electronic_ISBN
    2378-363X
  • Type

    conf

  • DOI
    10.1109/INDIN.2015.7281743
  • Filename
    7281743
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3662311