Title :
Differential current-mode clock distribution
Author :
Riadul Islam;Hany Fahmy; Ping-Yao Lin;Matthew R. Guthaus
Author_Institution :
Department of CE, University of California Santa Cruz, 95064, USA
Abstract :
In this paper, we present a differential current-mode pulsed flip-flop (DCMPFF) for low-power clock distribution using a representative 45nm CMOS technology. Experimental results show that the DCMPFF has 47% faster clock-to-output (CLK-Q) delay than a traditional voltage-mode (VM) pulsed flip-flop. When the DCMPFF is integrated with a differential current-mode clock distribution, the differential technique saves 62% and 17% power compared to a conventional VM and a previous current-mode (CM) clock network, respectively.
Keywords :
"Clocks","Delays","Integrated circuit interconnections","Power demand","Noise","Synchronization","System-on-chip"
Conference_Titel :
Circuits and Systems (MWSCAS), 2015 IEEE 58th International Midwest Symposium on
DOI :
10.1109/MWSCAS.2015.7282042