Digitally programmable offset compensation of comparators in flash ADCs for hybrid ADC architectures

This paper presents an offset calibration approach that exploits the dynamic characteristics of a comparator to achieve a wide linear tuning range by placing varactors at two different internal nodes: the drains of the input pairs (D_i nodes) for high linearity, and the output nodes for wider compensation range. The comparators are placed in a 3-bit 1GS/s flash ADC that will be integrated into an 8-bit hybrid ADC architecture. A digital calibration scheme controls the gate voltages of the varactors and detects the minimum offset condition. The proposed configuration was simulated with a transistor-level flash ADC design in 0.13μm CMOS technology and a Verilog-A behavioral implementation of the calibration circuitry. The ADC consumes 1.48mW of power (excluding the calibration circuitry, flip-flops and encoder) from a 1.2V voltage supply. Monte Carlo simulation results indicate that the method reduces the 3-sigma input offset of the comparator from 36.9mV to 1.6mV. The simulated effective number of bits (ENOB) of the flash ADC is 2.96 bits.