A process tolerant semi-self impedance calibration method for LPDDR4 memory controller

This paper presents a novel process variation compensation technique for semi-self impedance calibration of the transmission line driver implemented with the Low Voltage Swing Terminated Logic (LVSTL). The impedance calibration in the pull-up and pull-down networks of the driver circuits are analyzed and designed based on the JEDEC LPDDR4(Low Power Double Data Rate) standard. Based on the impedance mismatch analysis, a new semi-self impedance calibration circuit for LPDDR4 is proposed to compensate the driver impedance mismatch caused by the process variation using process monitoring circuit. The proposed circuit is designed and implemented with 180nm CMOS technology using 1.8V supply voltage. With the proposed semi-self calibration circuit, ± V_OH level change due to process variations is reduced by 81% in pull-up and 74% in pull-down networks without power overhead because it is foreground calibration scheme.