Low power block matching using pattern based pixel truncation

A power efficient block matching algorithm is proposed using pattern based pixel truncation scheme. Our observation shows that during block matching, if we represent the block matching process as a one-dimensional signal, we can see clearly that the signal has repeated mountain- and valley-like regions. Utilizing this feature, the proposed low power block matching scheme truncates pixels except the pixels of the valley-like SAD values, which have high chance to be the minimum SAD value. We synthesized the proposed algorithm to measure the switching power dissipation. The results show that the proposed BMA architecture obtains at least 76% power saving with negligible coding performances.