Simplified Volterra series based background calibration for high speed high resolution pipelined ADCs

This paper introduces a simplified dynamic deviation reduction (DDR) based Volterra series model for calibrating high speed high resolution pipelined analog-to-digital converters (ADCs) because the memoryless polynomial model may not be accurate enough due to memory effects often occur in these types of ADCs. A correlation based background calibration, with pseudorandom bit sequence (PRBS) injection in the analog domain, is proposed to extract the coefficients of the DDR based model. Simulation results demonstrate that excellent calibration performance can be achieved for a 12-bit ADC with memory effects in the first stage amplifier.