Bitwidth-aware register allocation and binding for clock period minimization

With the growing scale of integration, it is demand for next-generation VLSI design to consider not only the number of resources, but also the bitwidths of them. Removing wasted bits of resources, the area and power costs are optimized rather than conventional design. This paper shows that intentional clock skew (useful clock skew) is effective to improve the performance of bitwidth-aware circuits, and formulates a novel problem of clock skew scheduling to minimize the clock period during register allocation and binding under the total bitwidth constraint. A mixed integer linear programming-based approach is presented to formally draw up the problem. Experimental results show that the proposed approach can reduce 9.4% clock period on average over the conventional design.