Modeling and design of a 0.8–30 GHz tunable inductor-less divide-by-2 frequency divider with digital frequency calibration

In this paper, a novel analytical model for current-mode-logic D flip-flop (CML-DFF) frequency divider is presented. With the help of this model, a tunable inductor-less divide-by-2 CML-DFF divider operating from 0.8-30 GHz with digital frequency calibration is designed and simulated in TSMC 90 nm CMOS process. The proposed divider has a tunable frequency locking range of 190% at peak-to-peak injection voltage of 600 mV. The divider consumes 2.94 mA from a 1.2 V supply. The total area of this divide-by-32 divider chain with digital frequency calibration is less than 0.04 square millimeter.