0.25–4 ns 185 MS/s 4-bit pulse-shrinking time-to-digital converter in 130 nm CMOS using a 2-step conversion scheme

An area and power efficient pulse-shrinking delay-line time-to-digital converter (TDC) using a 2-step conversion scheme is presented. The proposed TDC quantizes time variables using a coarse pulse-shrinking TDC with a large per-stage time shrinkage and a fine pulse-shrinking TDC with a small per-stage time shrinkage. It offers low power and silicon consumption, and good linearity without sacrificing resolution. The proposed TDC has been designed in an IBM 130 nm 1.2 V CMOS technology. The input range of the TDC is 4 ns, conversion rate 185 MS/s, resolution 250 ps, INL of 1 LSB, and figure-of-merit 0.163 pJ/conv.step.