A 12.88 MS/s 0.28 pJ/conv.step 8-bit stage-interleaved pulse-shrinking time-to-digital converter in 130 nm CMOS

An 8-bit stage-interleaved pulse-shrinking time-to-digital converter (TDC), aiming at minimizing silicon consumption, improving the linearity to minimize the number of fine TDCs and removing the speed penalty without sacrificing conversion time and resolution is proposed. The proposed TDC quantizes time variables using a 16-stage coarse pulse-shrinking TDC with resolution 4.8 ns. The residue of the coarse TDC is digitized by a fine 16-stage TDC with resolution 296 ps using a stage-interleaved approach. The proposed TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results demonstrate that the proposed TDC outperforms reported pulse-shrinking TDCs with 0.3-76.8 ns input range, 12.88 MS/s conversion rate, 0.78 LSB integral nonlinearity, and 0.28 pJ per conversion step.