An FPGA based passive k-delta-1-sigma modulator

An FPGA based 2^nd-order passive KD1S sigma-delta modulator was designed, simulated and tested. The design is implemented on an Altera Cyclone IV EP4CE115 FPGA. All active components such as digital logic, clock circuitry, and registers are located internally on the FPGA chip with only passive RC lumped analog components located off chip. The circuit uses eight logic elements and two PLL blocks on the FPGA to create an eight path KD1S sigma-delta modulator. The design performance was quantified at effective sampling rates of 80 MHz and 450 MHz. The implementation achieved a peak SNR of 58 dB and an ENOB of 9.3 bits at a 450 MHz effective sampling rate. The key benefit of this approach is the absence of active analog components, very low power, and high-speed sampling.