Efficient architecture and implementation for NTRUEncrypt system

NTRU has gained much attention recently because it is relatively efficient for practical implementation among the post-quantum public key cryptosystems. In this paper, an efficient hardware architecture and FPGA implementation of NTRUEncrypt is proposed. The new architecture takes advantage of linear feedback shift register (LFSR) structure for its compact circuitry and high speed. A novel design of the modular arithmetic unit is proposed to reduce the critical path delay. The FPGA implementation results have shown that the proposed design outperforms all the existing works in terms of area-delay product.