FPGA design space exploration of IDEA cryptography IP core

Securing data in machine to machine scenario is of paramount importance. With the evolving of Internet of Things (IoT) market, data should be protected from eavesdropper. Of the available cryptographic algorithms, International Data Encryption Algorithm (IDEA) is one of the most secured and highly accepted algorithm to a broad range of applications. This paper presents implementation of IDEA cryptographic IP core in two different application needs, and explores the tradeoffs of a RTL looping (least area, latency) implementation and a pipelined implementation. All the designs are implemented on Xilinx Virtex6 XC6VLX240T FPGA evaluation board and obtained the throughputs of 764.59 Mbps and 73.45 Mbps for pipelined designs and RTL looping, respectively.