DocumentCode :
3662695
Title :
Real-time VLSI architecture for palm rejection using Wronskian Determinant
Author :
Abu M Baker; Yingtao Jiang
Author_Institution :
Hewlett Packard, 11445 Compaq Center Dr W, Houston, TX 77070, USA
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
Several Human Interface Technology applications require reliable palm rejection. Palm rejection in upcoming touch or Pad technology has a need of hardware implementation with requirements of low power and small area. This paper introduces a hardware implementation of a real-time palm rejection based on Wronskian Determinant. This detection algorithm offers regularity, low complexity and accuracy as well as robustness against global illumination changes. The proposed architecture is able to process incoming frames on-the-fly, therefore requiring a small amount of memory. The maximum frame rate is 15 fps, however the implementation is flexible enough to allow analysis of less frames if required. Processing unit consist of a basic processing element implemented in pipeline fashion and adder tree to produce final results. The architecture was implemented using a XCV800 FPGA. The power consumption of the whole system is 93 mW.
Keywords :
"Process control","Field programmable gate arrays","Detectors","Image resolution","Adders","Solids"
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2015 IEEE 58th International Midwest Symposium on
Type :
conf
DOI :
10.1109/MWSCAS.2015.7282154
Filename :
7282154
Link To Document :
بازگشت