Runtime slack-deficit detection for a low-voltage DCT circuit

We present a deployment strategy for Error (slackdeficit) Detection Sequential (EDS) circuits to monitor non-critical paths of application systems at the clock falling edges, requiring neither buffer insertions nor extra clocks. The proposed strategy is applied to an FPGA-based Discrete Cosine Transform (DCT) unit together with EDS and Dynamic Voltage Scaling (DVS) circuits as a proof of concept. It is able to speculatively and accurately detect slack-deficits due to dynamic process, voltage and temperature (PVT) variations and correspondingly adjust the supply voltage. When processing realistic input data and operating at the same frequency as a highly-optimized baseline DCT implementation, our design produces equivalent outputs and incurs a 0.3% logic element overhead and 3.5% maximum frequency degradation, but saves up to 16.5% energy.