Revisiting redundant Booth with bias multipliers

Multiplication is an important mathematical operation in many microprocessor architectures. And, multipliers have evolved dramaticlly after the late 1970s and have gone through tremendous changes with an aim of reducing the area and delay. This paper presents and an extension to Booth-3 multiplication architecture by implementing the partial product matrix in redundant form. It is anticipated that by employing redundant encoding possibilities within larger operand sizes that the partial product matrix can be subtantially reduced. Further enhancements are presented to allow the multiplier to compute two´s complement numbers and clarification on previous algorithms to allow efficient sign extension with signed numbers is also presented. Results in a 65nm technology indicate that redundant Booth multipliers have the potential to improve upon traditional high radix Booth multiplication architectures.