An efficient high speed RISC processor for convolution

Many algorithms have been design in order to accomplish an improved the performance of the filters by using the convolution design. The architecture of the proposed RISC CPU is a uniform 32-bit instruction format, single cycle non-pipelined processor. It has load/store architecture, where the operations will only be performed on registers, and not on memory locations. It follows the classical von-Neumann architecture with just one common memory bus for both instructions and data. A total of 27 instructions are designed in initial development step of the processor. The instruction set consists of Logical, Immediate, Jump, Load, store and HALT type of instruction. The combined advantages RISC processor such as high speed, low power, area efficient and operation-specific design possibilities have been analyzed. In this paper we have implemented 32 bit RISC processor to perform circular convolution at different modules of RISC processor like execute unit along with ALU, Instruction fetch along with instruction memory, decode unit, resistor unit, data memory has been implemented. The execution time to perform 4 bit circular convolution is found to be 270 ns. The execution time to execute the instruction is found to be 5 ns. In our paper, 3200 LUTs and 320 logic elements are used to implement 32 bit RISC processor which is found to be area efficient as compared to various designs.