DocumentCode :
3663966
Title :
Hi-fi playback: Tolerating position errors in shift operations of racetrack memory
Author :
Chao Zhang;Guangyu Sun;Xian Zhang;Weiqi Zhang;Weisheng Zhao;Tao Wang;Yun Liang;Yongpan Liu;Yu Wang;Jiwu Shu
Author_Institution :
Center for Energy-efficient Computing and Applications, Peking University, Beijing, 100871, China
fYear :
2015
fDate :
6/1/2015 12:00:00 AM
Firstpage :
694
Lastpage :
706
Abstract :
Racetrack memory is an emerging non-volatile memory based on spintronic domain wall technology. It can achieve ultra-high storage density. Also, its read/write speed is comparable to that of SRAM. Due to the tape-like structure of its storage cell, a “shift” operation is introduced to access racetrack memory. Thus, prior research mainly focused on minimizing shift latency/energy of racetrack memory while leveraging its ultra-high storage density. Yet the reliability issue of a shift operation, however, is not well addressed. In fact, racetrack memory suffers from unsuccessful shift due to domain misalignment. Such a problem is called “position error” in this work. It can significantly reduce mean-time-to-failure (MTTF) of racetrack memory to an intolerable level. Even worse, conventional error correction codes (ECCs), which are designed for “bit errors”, cannot protect racetrack memory from the position errors. In this work, we investigate the position error model of a shift operation and categorize position errors into two types: “stop-in-middle” error and “out-of-step” error. To eliminate the stop-in-middle error, we propose a technique called sub-threshold shift (STS) to perform a more reliable shift in two stages. To detect and recover the out-of-step error, a protection mechanism called position error correction code (p-ECC) is proposed. We first describe how to design a p-ECC for different protection strength and analyze corresponding design overhead. Then, we further propose how to reduce area cost of p-ECC by leveraging the “overhead region” in a racetrack memory stripe. With these protection mechanisms, we introduce a position-error-aware shift architecture. Experimental results demonstrate that, after using our techniques, the overall MTTF of racetrack memory is improved from 1.33μs to more than 69 years, with only 0.2% performance degradation. Trade-off among reliability, area, performance, and energy is also explored with comprehensive discussion.
Keywords :
"Error correction codes","Random access memory","Parity check codes","Torque","Reactive power","Fitting","Current density"
Publisher :
ieee
Conference_Titel :
Computer Architecture (ISCA), 2015 ACM/IEEE 42nd Annual International Symposium on
Type :
conf
DOI :
10.1145/2749469.2750388
Filename :
7284105
Link To Document :
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