Fractional-N frequency synthesizer and RF receiver front-end for wireless communications application

This paper presents a 0.18 μm CMOS low-power fractional-N frequency synthesizer with a sub-sampling charge pump (SSCP) circuit and a randomly selected PFD to reduce reference spur and RF receiver front-end applying wireless communications systems is presented. The proposed RF receiver front-end includes a current-reused LNA, a folded Giber cell mixer, a Colpitts VCO, and an IF Gm-C bandpass filter. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage controlled oscillator to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control for IoT networks and communications application.