An area-efficient 1.5-GHz dual-VDD 4-port register file for real-time microprocessors

An area-efficient 4-port register file is presented for real-time microprocessors. Bitcell area efficiency is achieved with one-sided read operations and single-ended write operations together with an additional higher voltage source for write operations. High bitcell stability is maintained with one-sided read operations when the supply voltage is scaled down to 0.7V. Array-wide power savings are achieved in the standby mode with modifications to peripheral logic. A 32-entry × 64-bit/word register file is designed in 1.2V TSMC 65nm low power triple-V_t CMOS technology. The proposed bitcell occupies 35.4% less silicon area and the proposed array consumes 17.5% lower standby power when compared to the conventional 4-port dual-V_t register file. These benefits are achieved by trading off bitcell read and write noise margins and 10% performance at the lower end of the operating voltage range.