DocumentCode :
3664724
Title :
The path finding of gate dielectric breakdown in advanced high-k metal-gate CMOS devices
Author :
Steve Chung
Author_Institution :
Department of Electronics Engineering, National Chiao Tung University, Taiwan
fYear :
2015
fDate :
6/1/2015 12:00:00 AM
Firstpage :
360
Lastpage :
364
Abstract :
The breakdown path induced by BTI stress in a MOSFET device can be traced from the experiment. It was demonstrated on advanced high-k metal gate CMOS devices. RTN traps in the dielectric layers can be labeled as a pointer to trace the breakdown path, i.e., from the leakage by measuring the Ig current as a function of time. It was found that breakdown path tends to grow from the interface of HK/IL or IL/Si which is the most defective region. Two types of breakdown paths will be presented. The soft-breakdown path is in a shape like spindle, while the hard breakdown behaves like a snake-walking path. These two breakdown paths are reflected in a two slopes TDDB lifetime plot. These new findings on the breakdown-path formation will be helpful to the understanding of the reliability in HK CMOS devices.
Keywords :
"Logic gates","Electron traps","Electric breakdown","Dielectrics","MOSFET circuits","Current measurement","Dielectric measurement"
Publisher :
ieee
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International Conference on
Print_ISBN :
978-1-4799-8362-9
Type :
conf
DOI :
10.1109/EDSSC.2015.7285125
Filename :
7285125
Link To Document :
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