• DocumentCode
    3664730
  • Title

    Investigation of low temperature Cu/In bonding in 3D integration

  • Author

    Yu-Sheng Hsieh;Ting-Ting Shen;Yu-San Chien;Kuan-Neng Chen;Yuko Shinozaki;Naohiko Kawasaki

  • Author_Institution
    Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan
  • fYear
    2015
  • fDate
    6/1/2015 12:00:00 AM
  • Firstpage
    383
  • Lastpage
    386
  • Abstract
    Low temperature (<; 180 °C) Cu/In bonding scheme in wafer-level is successfully developed. The bonded sample represents robust bonding quality and passes mechanical tests. The inter-diffusion mechanism and IMC phases are investigated by EDX and EELS. In addition, the specific contact resistance of Cu/In chip is measured approximately 3 × 10-9 Ω-cm2 by modified Kelvin feature, demonstrating excellent electrical characteristics. Good stability is also observed from reliability tests, including current stressing, TCT and un-bias HAST. Therefore, this low temperature Cu/In bonding scheme provides a promising method for dense vertical interconnects.
  • Keywords
    "Conferences","Electron devices","Solid state circuits"
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International Conference on
  • Print_ISBN
    978-1-4799-8362-9
  • Type

    conf

  • DOI
    10.1109/EDSSC.2015.7285131
  • Filename
    7285131
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3664730