A low-energy high-throughput asynchronous AES for secure smart cards

AES has been widely used in current financial security application, but side-channel attacks are considered as serious threats to AES cryptographic algorithm. Asynchronous AES design will be a potential solution because of its natural properties. First, our asynchronous AES architecture, round key generation architecture and mix column calculation architecture are proposed. Then, properties of Balsa HDL are investigated and exploited to reduce area and power, followed by GTECH-based design flow is described. Finally, a VLSI implementation of our AES crypto-processor is carried out with TSMC 130 nm CMOS technology. Experimental results show that our proposed asynchronous AES architecture can respectively achieve 67.7% and 40% lower ciphering time and power delay product of its counterpart, and its area is only 7.3% and 15% of those reported in other papers. Moreover, it can be easily integrated into an asynchronous security chip.