DocumentCode
3664757
Title
Bottom-up meets top down: An integrated approach for nano-scale devices
Author
V. Ramgopal Rao;Tejas R. Naik;Rajul S. Patkar
Author_Institution
Dept. of Electrical Engineering, Indian Institute of Technology Bombay (IIT Bombay)
fYear
2015
fDate
6/1/2015 12:00:00 AM
Firstpage
491
Lastpage
494
Abstract
Conventional CMOS and MEMS technologies usually employ top-down fabrication methodologies for high volume manufacturing. However, as the CMOS technologies are scaled down, there are many challenges owing to its variability, reliability and power issues. Some of these issues in CMOS and MEMS technologies can be better addressed by employing a host of bottom-up nanotechnology approaches through innovative process integration strategies. This calls for an intelligent integration of diverse technologies, materials and processes on the same die or in a package for realization of future smart systems. Here we present some of these integration methodologies where completely diverse platforms, materials and approaches are brought together in order to realize a targeted system functionality.
Keywords
"Conferences","Electron devices","Solid state circuits"
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International Conference on
Print_ISBN
978-1-4799-8362-9
Type
conf
DOI
10.1109/EDSSC.2015.7285158
Filename
7285158
Link To Document